1. Field of the Invention
This invention relates to a multilayer printed wiring board used as a package board for mounting an IC chip or the like and a process of producing the same, and more particularly to a multilayer printed wiring board capable of providing a high density wiring easily and of preventing the formation of cracks or the like in through-holes or in the neighborhood thereof when heat cycle occurs, for example.
This invention also relates to a resist composition for filling through-hole of a multilayer printed wiring board, which composition is used for ensuring satisfactory electric connections between viaholes and through-holes even at high temperature and high humidity conditions or under such conditions as to cause heat cycle.
2. Discussion of Background Information
In general, through-holes are formed for electrically connecting the front surface to the back surface of a core substrate (hereinafter referred to as “substrate”) of a two-sided multilayer printed wiring board. These through-holes are, however, considered as dead spaces in designing of a circuit, and hence become one of the factors which prevent wiring from densifying.
To reduce such dead spaces, the prior art has applied, for example, the following technologies;
Japanese Unexamined Patent Publication No. 9-8424 discloses a technique of filling through-holes with a resin and roughening the resin on its surface and forming a mount pad on the roughened surface.
Japanese Unexamined Patent Publication No. 2-196494 discloses a technique of filling through-holes with a conductive paste, and dissolving and removing an electrolytic plated film covering the through-holes to form landless through-holes.
Japanese Unexamined Patent Publication No. 1-143292 discloses a technique of filling through-holes with a conductive paste and subjecting the resultant substrate to a copper plating to form a plated film covering the paste.
Japanese Unexamined Patent Publication No. 4-92496 discloses a technique of forming, for example, a copper plated film onto all over the surface of a substrate inclusive of internal surfaces of through-holes by electroless plating, filling the inside of the through-holes with an electrically conductive material (conductive paste) and then covering the substrate with a copper plated film so as to encapsulate the electrically conductive material in the through-holes.
The conventional techniques mentioned above, however, have the following disadvantages.
A two-sided multilayer printed wiring board as is described in Japanese Unexamined Patent Publication No. 9-8424 requires a roughening treatment of the surface of a resin in order to ensure adhesion between the resin filled in through-holes and the mount pad. In addition, since coefficients of thermal expansion between the resin and a metal are different, the conductor layer on the through-holes may peel or form cracks due to heat cycle.
According to the technique described in Japanese Unexamined Patent Publication No. 2-196494, when openings for viaholes are formed just above the through-holes of an interlaminar resin layer with a laser beam, the conductive paste is exposed to the openings and thereby a resin ingredient in the conductive paste is also eroded.
In a printed wiring board as is described in Japanese Unexamined Patent Publication No. 1-143292, the conductive paste is in direct contact with the internal surfaces of through-holes of a resin substrate so that metal ions are apt to disperse from the surfaces to the inside of the substrate when it takes up moisture. The dispersion (migration) of metal ions causes development of a short circuit between the conductor layer and the through-holes.
In a printed wiring board as is described in Japanese Unexamined Patent Publication No. 4-92496, gaps or voids tend to form because of poor adhesion between the conductor layer and the electric conductive material in the through-holes. The formation of voids between the electric conductive material and a through-hole causes delamination of the conductor layer or generation of cracks on the through-hole in the use at high temperature and high humidity conditions due to air or water accumulated in the voids.
In some instances, it may be desired to connect a through-hole to a viahole formed on a substrate. In this case, connection is generally made by forming a pad, i.e., a land protrusion on the periphery of the through-hole, and connecting the through-hole to the viahole through the interposition of the pad. The pad is, however, frequently obstructive because it is formed protruding on the outer periphery of the through-hole and hence causes, for example, an increasing pitch between adjacent through-holes to each other. This becomes an impediment to achieving a high density wiring or to narrower intervals between through-holes.
On the contrary, examples of conventional multilayer wiring boards having a high density wiring function are the following Japanese Unexamined Patent Publications:
Japanese Unexamined Patent Publication No. 6-275959 discloses a multilayer printed wiring board obtained by filling through-holes with a filler, forming a conductor layer thereon, and forming viaholes on the conductor layer. Japanese Unexamined Patent Publication No. 5-243728 discloses a process of filling through-holes with a conductive paste and curing the paste, polishing a surface of the substrate, forming a conductor layer covering the through-holes, and mounting a surface mount part on the conductor layer.
According to these conventional techniques, a surface mount part can be connected to through-holes so as to provide high density wiring or through-holes, but they have the following disadvantages.
The multilayer printed wiring board as exemplified in Japanese Unexamined Patent Publication No. 6-275959 is obtained by filling through-holes with a photosensitive resin as the filler. In such a wiring board, delamination between the filler and the conductor layer occurs when the wiring board is exposed to high temperature and high humidity conditions such as in Pressure Cooker Test, and a reliable connection between viaholes formed on the conductor layer and through-holes cannot be obtained.
The technique disclosed in Japanese Unexamined Patent Publication No. 5-243728 is not a technique relating to a build-up multilayer printed wiring board and hence does not make the most of the high density wiring function inherent in the build-up method.